This invention relates to a process for preparing a multi-layer printed wiring board, particularly to a process for preparing a multi-layer printed wiring board having on the same lattice a plurality of via holes formed by dividing a conductor layer which is part of a via hole on the same lattice for the purpose of high density mount.
For the purpose of making LSI, IC, etc. highly integrated, enhancing performances of electronic instruments and improving economical problems, higher densification of multi-layer printed wiring board (hereinafter abbreviated as multi-layer board) is in progress.
For higher densification of multi-layer boards, two measures have primarily been taken.
The first measure is increase of the number of conductor layers, namely multi-layer formation, and the second one is to multi-wiring between the basic lattices. However, the first measure will result in increase of via holes connecting the conductor layers between the layers, while in the multi-wiring according to the second measure, wiring capacity will be markedly limited. Accordingly, these inconveniences are compensated for by reducing via hole diameter, making wired conductor finer, etc., but all of these interfere with productivity of multi-layer boards.
As a method for solving this problem, there has been proposed a multi-layer board having buried via holes or surface (blind) via holes.
In the following, a representative preparation process is described by referring to FIG. 1 as an example.
First, as shown in FIG. 1(A), a laminated board is drilled and panel-plated to form a via hole as a surface via hole 14, and next, an internal layer circuit pattern 15 is formed only on one surface according to the photo-printing method to prepare a surface via internal layer board 16.
Similarly, as shown in FIG. 1(B), a laminated board is drilled and panel-plated to form a via hole as a buried via hole 17, and next, internal layer circuit patterns 15a and 15b are formed on the both surfaces according to the photoprinting method to prepare a buried via internal layer board 18.
In the next step, as shown in FIG. 1(C), the previous two kinds of internal layer boards 16, 18, 16a are set with prepregs 7 and 7a being interposed, and via the heating and pressurizing steps as shown in FIG. 1(D), a multi-layer molded substrate with each internal layer board being integrated with a prepreg layers 10 and 10a is obtained.
Next, as shown in FIG. 1(E), at the predetermined sites on a multi-layer molded substrate 11 are perforated penetrated holes, which are applied with panel plated layers 19, 19a and 19b to form a penetrated via hole 12, followed by photoprinting process, thereby obtaining a multi-layer printed wiring board 13 having surface via holes 14 and 14a and a buried via hole 17 according to the preparation process of the prior art.
Also there has been known a method, in which at the surface via holes are formed conventional copper-clad multi-layer boards, and from the external layer surface are perforated half-penetrated holes by L/C driller, laser process, etc., and then conventional panel plating and photo-printing are applied to connect the external layer and the internal layer immediately below the external layer through the half-penetrated hole, thereby obtaining surface via holes (not shown).
The preparation process of the prior art as described above has the following drawbacks.
First, a resin to be filled within the surface via holes and the buried via hole is accounted for only by the resin contained in the prepregs. Therefore, the thickness of the internal layer board can be obtained only to the extent which is the same as the prepreg layer, and the thickness of this kind of internal layer board is about 0.3 to 0.4 mm at the maximum, whereby multi-layer formation has been almost impossible.
Accordingly, when via holes are generally formed on the same lattice with a multi-layer board including more than 10 layers in a double-sided internal board, there are only two kinds of methods broadly classified, namely the method of forming surface via holes and buried via holes, or forming penetrated through holes and using them as via holes. Particularly, in the case of the penetrated via holes of the latter, only one hole can be arranged on one lattice point, causing the problem of via hole neck becoming more disadvantageous as more multiple layer formation is attempted.
An object of the present invention is to provide a process for preparing a multi-layer printed wiring board which overcomes the via hole neck problem which becomes more disadvantageous as more multiple layer formation is attempted.